//`timescale 1ns/1ns

module test;
   reg rst;
   reg clk;
   wire [7:0] count;

   counter counter1(.rst(rst), 
		    .clk(clk), 
		    .count(count));

   always #5 clk = ~clk;
   initial begin
      rst = 1;
      clk = 0;
      #10 rst = 0;
   end

   initial begin
      //$hello;		//defined by pli
      #60 $finish;
   end

   initial $hello_param(3);
   always@(posedge clk) $hello;

   initial $show_nets(test);
   initial $show_nets(counter1);

endmodule // test

module counter(rst, clk, count);
   input rst, clk;
   output reg[7:0] count;

   always@(posedge rst or posedge clk)
     begin
	if(rst)
	  count <= 0;
	else
	  count <= count + 1;
     end
endmodule // counter
